1. Field of the Invention
The present invention relates to a semiconductor device with a plurality of through substrate vias, and more particularly to a semiconductor device with a plurality of mark through substrate vias.
2. Description of the Related Art
FIG. 1 shows a schematic cross-sectional view of a conventional semiconductor wafer. FIG. 2 shows a partially cross-sectional view of FIG. 1. The semiconductor wafer 1 includes a semiconductor substrate 10 and a plurality of through substrate vias 12. The semiconductor substrate 10 has a front surface (not shown) and a backside surface 101. The through substrate vias 12 are disposed in the semiconductor substrate 10, and the back ends 121 of the through substrate vias 12 protrude from the backside surface 101.
After an exposure process, the position and direction on the backside surface 101 of the semiconductor substrate 10 must be identified to continue the following steps, such as: a photoliography process, which is used to form a redistribution layer (RDL) on the backside surface 101. A special backside alignment (BSA) equipment is used to achieve the intention. However, the use of such equipment will raise the manufacture cost, and the alignment error is high.
FIG. 3 shows a schematic cross-sectional view of a conventional semiconductor die. The semiconductor die 2 is cut form a semiconductor wafer. The semiconductor die 2 includes a semiconductor substrate 20, a backside passivation 21 and a plurality of through substrate vias 22. The semiconductor substrate 20 has a front surface (not shown) and a backside surface 201. The backside passivation 21 is disposed on the backside surface 201. The through substrate vias 22 are disposed in the semiconductor substrate 20 and the back ends 221 of the through substrate vias 22 protrude from the backside surface 201 and the backside passivation 21. A surface finish layer 222 is formed on the back ends 221 of the through substrate vias 22.
In a semiconductor process, a top semiconductor device (not shown) is bonded to the backside surface 201 of the semiconductor substrate 20, and the protruded back ends 221 of the through substrate vias 22 must contact the bumps or solder balls on the bottom surface of the top semiconductor device for electrical connection. Before the bonding process, the position and direction on the backside surface 201 of the semiconductor substrate 20 must be identified. Usually, a redistribution layer (RDL) is formed on the backside surface 201 to serve as a fiducial mark. The fiducial mark is easily to be detected, which facilitates identifying the position and direction on the backside surface 201. However, the formation of the RDL will raise the manufacture cost.
Therefore, it is necessary to provide a semiconductor device with a plurality of mark through substrate vias to solve the above problems.